library ieee; use ieee.std_logic_1164.all; -- use ieee.std_logic_unsigned.all; -- parallel shift register with asynch. reset entity REG is port ( CLK : in std_logic; LOAD : in std_logic; RESET : in std_logic; DI : in std_logic; SI : in std_logic; SO : out std_logic ); end REG; architecture REG_BODY of REG is begin P: process (CLK, RESET) variable output: std_logic := 'U'; begin if RESET = '1' then output := '0'; elsif CLK'event and CLK = '1' then -- raising clk edge if LOAD = '1' then -- parallel output := DI; else -- serial output := SI; end if; -- serial or parallel end if; -- output SO <= output; end process; end REG_BODY; -- ----------------------------------------------------- TEST library ieee; use ieee.std_logic_1164.all; entity TEST_REG is end TEST_REG; -- 3 bit reg architecture TEST_REG_BODY of TEST_REG is signal CLK : std_logic; signal LOAD : std_logic; signal RESET : std_logic; signal DI : std_logic_vector (2 downto 0); signal SI : std_logic; signal SO0 : std_logic; signal SO1 : std_logic; signal SO2 : std_logic; -- component REG port ( CLK : in std_logic; LOAD : in std_logic; RESET : in std_logic; DI : in std_logic; SI : in std_logic; SO : out std_logic ); end component; -- begin -- components bit0: REG port map (CLK, LOAD, RESET, DI(0), SI, SO0); bit1: REG port map (CLK, LOAD, RESET, DI(1), SO0, SO1); bit2: REG port map (CLK, LOAD, RESET, DI(2), SO1, SO2); -- processes TEST: process begin RESET <= '0'; LOAD <= '0'; SI <= '1'; SI <= '0'; wait for 20 ns; SI <= '1'; wait for 20 ns; SI <= '0'; wait for 20 ns; LOAD <= '1'; DI <= "010"; wait for 20 ns; RESET <= '1'; SI <= '1'; -- shall have no effect wait for 100 ns; end process TEST; P_CLK: process -- period T = 20 ns (15+5) begin CLK <= '0'; wait for 15 ns; CLK <= '1'; wait for 5 ns; end process P_CLK; end TEST_REG_BODY;